1. Field of the Invention
The present invention relates to a semiconductor memory device with its data storage state changing in accordance with a voltage applied to a bit line connected to the device and relates to a method for operating the device.
2. Description of the Related Art
There is known a nonvolatile memory device including a data storage element with a data storage state which changes in accordance with a voltage applied to a bit line connected to the device.
Representative examples of a memory device are volatile memory devices such as DRAMs (Dynamic Random Access Memories) and SRAMs (Static Random Access Memories). Another representative example of the memory device is a nonvolatile (flash) EEPROM (Electrically Erasable Programmable Read Only Memory) represented by an FG (Floating Gate)-type memory. For more information, the reader is requested to refer to Japanese Patent No. 3142335 (hereinafter referred to as Patent Document 1).
By the way, there is also a nonvolatile memory device which allows data stored in the device to be updated at a high speed. Such a nonvolatile memory device can be used as an FG-type (flash) EEPROM which allows data stored in the FG-type (flash) EEPROM to be updated at a high speed. A typical example of such a nonvolatile memory device is a variable-resistance memory device which draws much attention.
As a typical example of such a variable-resistance memory device, there is known the so-called ReRAM (Resistance Random Access Memory) having a data storage state changed by a resistance variation which is obtained as a result of supplying conductive ions to a conductive film employed in a data storage element of the variable-resistance memory device and drawing conductive ions from the conductive film. For more information on the ReRAM, the reader is requested to refer to Japanese Patent. Laid-Open No. 2007-133930 (hereinafter referred to as Patent Document 2) or document such as K. Aratani, et al., “A Novel Resistance Memory with High Scalability and Nanosecond Switching,” Technical Digest IEDM 2007, pp. 783-786 (hereinafter referred to as Non-Patent Document 1).
As another example of the variable-resistance memory device, there is known a variable-phase memory device in which a phase variation occurring at a crystallization time of a conductive film employed in a data storage element of the variable-resistance memory device is controlled by the magnitude of a current flowing through the variable-resistance memory device and the length of the flowing time of the current. For more information on the variable-phase memory device, the reader is requested to refer to Japanese Patent Laid-Open No. 2006-302465 (hereinafter referred to as Patent Document 3).
As further examples of the variable-resistance memory device, there are known an MRAM (Magnetoresistive Random Access Memory) and a spin injection memory. That is to say, the MRAM and the spin injection memory can be classified as memory devices that have the same type as the variable-resistance memory device. The MRAM is a memory device in which the direction of magnetization of a magnetic film employed in the memory device is determined by the direction of a current flowing through the memory device and the magnitude of the current.
The variable-resistance memory devices including the (flash) EEPROM pertain to a category of nonvolatile memory devices in each of which the data storage state of a data storage element employed by the device changes in accordance with a voltage applied to a bit line connected to the device.
The (flash) EEPROM employs a memory transistor which serves as a data storage element. In the (flash) EEPROM, the data storage state of the data storage element changes due to injection of electric charges into a charge trap or an FG (Floating Gate) created in a gate insulation film.
With miniaturization of the data storage element, however, injection of electric charges becomes difficult to control. In addition, in order to implement a multi-value memory, the so-called write-verify operation is normally carried out. For details, the reader is requested to refer to Patent Document 1.
Even in a variable-resistance memory device such as the ReRAM, a verify operation may be carried out at a data write or erase time in some cases. This is because there are cases in which post-write data or post-erase data depends on the number of times the data update (that is, write or erase) operation is carried out. In the case of a variable-resistance memory device, the post-write data or the post-erase data is represented by the resistance of a data storage element employed in the device. For more information, the reader is requested to refer to Patent Document 2.
Patent Document 2 discloses a high-speed sequence of operations excluding a pre-charge process supposed to be carried out after a data write operation. That is to say, after a write bias for the data write operation has been removed, a read-to-verify operation based on electric charge stored on a bit line connected to the variable-resistance memory device is carried out.
To put it in detail, Patent Document 2 discloses a technology, in accordance with which a verify operation is carried out after a data write or erase operation by reading out post-write data or post-erase data in order to determine whether or not the data write or erase operation has been carried out with a high degree of sufficiency. The process of determining whether or not the data write or erase operation has been carried out with a high degree of sufficiency is referred to as a verify process. By carrying out the sequence of the data write or erase and verify operations repeatedly in accordance with this technology, it is possible to prevent an incorrect data write or erase operation from being performed. With regard to the verify operation, inhibit control that can be executed by a simple circuit and with a high degree of reliability is of importance. The inhibit control is control to inhibit the next verify operation if the result of the present verify operation indicates that the data write or erase operation has been carried out successfully.
Patent Document 1 discloses a (flash) EEPROM including a bit-line control circuit which employs a data latch/sense amplifier for latching data to be written into a data storage element employed in the EEPROM and for sensing data read out from the data storage element. By employing the data latch/sense amplifier for latching data to be written into a data storage element employed in the EEPROM and for sensing data read out from the data storage element, the size of a verify-operation control circuit can be reduced.
Patent Document 3 discloses a variable-phase memory device carrying out a selective reset operation by utilizing data latched in a data latch circuit which also functions as a data sense amplifier. The selective reset operation is an operation carried out in order to set a bit-line voltage for the next data write operation. The selective reset operation is carried out not for the purpose of verification, but for the purpose of making sequential random accesses. The data latch circuit functions also as a data latch amplifier for latching data to be written into the data storage element.